1. Technical Field
The present invention relates to a design support system of a semiconductor integrated circuit, a method of designing a semiconductor integrated circuit, a design support program of a semiconductor integrated circuit, and a method of manufacturing a semiconductor integrated circuit.
2. Description of Related Art
In a design of a semiconductor integrated circuit, a cell or a block which has a logic function and a storing function is disposed in a chip, their input/output terminals are wired respectively and a pattern layout on a chip area is thus determined in order to obtain a desirable circuit operation. A semiconductor integrated circuit using a general gate array method is constituted by a region in which a cell is to be disposed, a region in which a wiring between the cells is provided and a region in which an input/output circuit provided on a periphery is disposed. A plurality of wiring layers can be utilized for the wiring on the chip and other layers can be assigned to wirings in horizontal and vertical directions, respectively. In a layout design of the semiconductor integrated circuit, an arrangement of a cell and a wiring between terminals are automatically optimized by using a calculator to determine a layout pattern over a whole surface of a chip area (for example, see JP-A-11-265940).
In recent years, a microfabrication of dimensions of a transistor and a wiring which are to be manufactured on a wafer has been advanced and it has been hard to execute a manufacturing process in accordance with a design pattern intended in the beginning. A technique for forming a fine hole on an interlayer insulating film over a semiconductor substrate and processing a via for connecting wirings of upper and lower layers has also become increasingly hard. For this reason, a circuit pattern on a wafer which is actually manufactured is greatly influenced by a factor for a fluctuation in a manufacture, resulting in a poor reliability of an electrical connection so that a deterioration in a yield is caused. In a technology after the generation of a gate length of 130 nm, particularly, a rate of defects caused by a connecting failure of a via hole has been increased. By using a multi-cut via having a plurality of holes for a connection between wiring layers, therefore, it has been devised to decrease a probability of a failure as greatly as possible.
In a related-art automatic layout method, however, it is first supposed that a single via (a single cut via) is provided over a whole chip and a detailed wiring is provided, and a replacement with a multi-cut via is then carried out only in the case in which a permission can be made in consideration of a peripheral layout situation. More specifically, in the conventional automatic layout method, there is not considered a consumption of an adjacent wiring region which is caused by the provision of the multi-cut via in a wiring path search stage. For this reason, it is impossible to carry out a global optimization of a wiring processing on the assumption of the provision of the multi-cut via. Even if a wiring interval is increased by using a wire spreading function, it is hard to carry out a replacement of the multi-cut via in a place in which the bend of a wiring segment at a minimum interval between adjacent wirings defined in a predetermined process and a crank of a parallel wiring locally concentrate. Thus, there is a limit to optimize a layout pattern having a bad influence on the manufacture of a semiconductor integrated circuit after the wiring processing.